The invention relates to an integrated memory having memory cells and reference cells.
Such an integrated memory in the form of a ferroelectric random access memory (FRAM) is described in U.S. Pat. No. 5,844,832. The reference cells are used to generate a reference potential on bit lines in the memory before one of the memory cells is accessed. The memory cells are selected by word lines connected to them, while the reference cells are selected by reference word lines connected thereto.
It is generally known practice to provide integrated memories with redundant memory cells connected to redundant word lines for the purpose of repairing faults. By programming an appropriate logic unit, it is possible for the redundant word line having the redundant memory cells connected thereto to replace one of the normal word lines having the memory cells connected thereto on an address basis during operation of the memory.
It is accordingly an object of the invention to provide an integrated memory having memory cells and reference cells that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which has both normal memory cells and reference cells and in which faults can be repaired using redundant memory cells, the aim being to use as little space as possible for the redundant elements.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory containing bit lines, word lines intersecting the bit lines at points of intersection, and memory cells disposed at the points of intersection between the word lines and the bit lines. At least one reference word line is provided that intersects the bit lines at points of intersection and reference cells are disposed at the points of intersection between the at least one reference word line and the bit lines. The reference cells generate a reference potential on the bit lines before an access operation to one of the memory cells. A redundant word line is provided that intersects the bits lines at points of intersection, and redundant memory cells are disposed at the points of intersection between the redundant word line and the bit lines. A programmable activation unit has a programming state that governs if the redundant word line connected to the redundant memory cells replaces one of the word lines connected to the memory cells or the at least one reference word line connected to the reference cells during the operation of the integrated memory.
The integrated memory according to the invention is provided with redundant memory cells disposed at points of intersection between a redundant word line and bit lines in the memory. In addition, the memory has a programmable activation unit whose programming state governs whether the redundant word line having the redundant memory cells connected thereto replaces one of the word lines having the memory cells connected thereto or the reference word line having the reference cells connected thereto during operation of the memory.
Whereas, with conventional word line redundancy, a redundant word line can only be programmed to replace one of the normal word lines on an address basis, the integrated memory according to the invention has the option of choosing whether the redundant word line is to be used for this purpose or else for replacing one of the reference word lines. Hence, the invention permits a redundant word line and the redundant memory cells connected thereto to be used to repair both faults in normal memory cells and faults in reference cells or faults on the normal word lines or reference word lines connected to the latter. This results in much greater flexibility in the use of word line redundancy. If, by contrast, it were desirable to provide separate redundant word lines first for repairing faults on the normal word lines and second for repairing faults on one of the reference word lines, the integrated memory would need to have a greater number of redundant word lines than the memory according to the invention. This is because the invention is based on recognition of the fact that, although a memory has a large number of normal word lines, it has only an extremely small number, namely one or two, for example, of reference word lines for each memory block. The probability of one of the reference word lines having a fault is therefore much lower than that of a fault arising on one of the normal word lines.
Providing separate redundant word lines to repair the normal word lines, in the first instance, and to repair the reference word lines, in the second instance, would therefore be ineffective. By providing a common redundant word line for selectively repairing one of the normal word lines or one of the reference word lines, the number of redundant word lines can therefore be kept relatively small in the case of the invention, so that the space requirement therefor is likewise small.
In accordance with an added feature of the invention, the programmable activation unit has a first subunit and a second subunit connected to the first subunit. The first subunit is used to distinguish if the redundant word line replaces one of the word lines or the reference word line during the operation of the integrated memory. The second subunit determines an instant at which the redundant word line is activated by the programmable activation unit during the access operation to one of the memory cells. If the reference word line is replaced by the redundant word line, the second subunit activates the redundant word line for generating the reference potential, before one of the word lines is activated. If one of the word lines is being replaced by the redundant word line, the second subunit does not activate the redundant word line until after the reference word line has been activated for generating the reference potential.
In accordance with one development of the invention, the activation unit in the integrated memory has a first subunit, which is used to distinguish whether the redundant word line replaces one of the word lines or the reference word line during operation of the memory. In addition, the activation unit has a second subunit, which determines the instant at which the redundant word line is activated by the activation unit. For this purpose, during an access operation to one of the memory cells, when the reference word line is being replaced by the redundant word line, the second subunit activates the latter, for the purpose of generating the reference potential, before one of the word lines is activated. When one of the word lines is being replaced by the redundant word line, the second subunit does not activate the latter until after the reference word line has been activated for the purpose of generating the reference potential.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory having memory cells and reference cells, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.